Run-time Reconfigurable Instruction Set Processor (Rt-risp): Design and Simulation Using Verilog-hld - Shoab Ahmed Khan - Böcker - LAP LAMBERT Academic Publishing - 9783847336778 - 5 januari 2012
Om omslag och titel inte matchar är det titeln som gäller

Run-time Reconfigurable Instruction Set Processor (Rt-risp): Design and Simulation Using Verilog-hld

Pris
SEK 659

Beställningsvara

Förväntad leverans 19 - 27 okt
Få avisering om nya utgåvor med Shoab Ahmed Khan
Lägg till din iMusic-önskelista
eller

Inte betygsatt ännu

Run-Time Reconfigurable Instruction Set Processors are next generation processors, which can optimize their instruction sets according to the demands of the applications being under execution on them. This optimization is achieved through reconfiguration in their hardware on fly. In this way the reconfigurable processors adapt their hardware, which is most suitable one for the running application and consequently they enhance the performance. Reconfigurable instruction set processors are the programmable processors that contain the reconfigurable logic in one or more of their functional units. The hardware design of such type of processors can be categorized into two main tasks: The design of reconfigurable logic itself and the design of the communication interface of reconfigurable logic with the remaining modules of the processor.

Media Böcker     Pocketbok   (Bok med mjukt omslag och limmad rygg)
Releasedatum 5 januari 2012
ISBN13 9783847336778
Utgivare LAP LAMBERT Academic Publishing
Antal sidor 184
Mått 150 × 11 × 226 mm   ·   292 g
Språk Tyska  

Fler produkter med Shoab Ahmed Khan